Automating elimination of idle functions by run-time reconfiguration
Department of Computing, Imperial College London, London, UK
21st IEEE International Symposium on Field-Programmable Custom Computing Machines, 2013
@article{niu2013automating,
title={Automating elimination of idle functions by run-time reconfiguration},
author={Niu, Xinyu and Chau, Thomas CP and Jin, Qiwei and Luk, Wayne and Liu, Qiang and China, Tianjin},
year={2013}
}
A design approach is proposed to automatically identify and exploit run-time reconfiguration opportunities while optimising resource utilisation. We introduce Reconfiguration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and run-time solution generation. Three applications, based on barrier option pricing, particle filter, and reverse time migration are used in evaluating the proposed approach. The run-time solutions approximate the theoretical performance by eliminating idle functions, and are 1.31 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 28.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs.
June 6, 2013 by hgpu
