high performance computing on graphics processing units: hgpu.org

This paper introduces an implementation of a parallel solution for the chip layout problem on an NVidia CUDA framework. The experiment allows for varying chip sizes, interconnecting signals, and three chip transformations: rotate, swap, and translate. Total signal distance is minimized as the system converges toward an optimal solution using simulated annealing. Lee’s maze routing algorithm is utilized in finding the shortest unblocked signal path between chips. OpenGL is used to visualize the chips and signals as they traverse through the annealing process. Results show that the speed of the parallel execution is limited by the memory capacity of the device and the problem size.