10569

Paralleling Variable Block Size Motion Estimation of HEVC on Multi- Core CPU Plus GPU Platform

Xiang-wen Wang, Li Song, Min Chen, Jun-jie Yang
Shanghai University of electric power
2013 IEEE International Conference on Image Processing, 2013
@article{wang2013paralleling,

   title={PARALLELING VARIABLE BLOCK SIZE MOTION ESTIMATION OF HEVC ON MULTI-CORE CPU PLUS GPU PLATFORM},

   author={Wang, Xiang-wen and Song, Li and Chen, Min and Yang, Jun-jie},

   year={2013}

}

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Motion estimation with variable block sizes (VBSME) is one of the most complex models in the HEVC encoder. The HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 for motion estimation (ME) and motion compensation (MC). This feature contributes substantial coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. The VBSME becomes the bottleneck for real time encoding. In this paper, we propose novel strategies for parallel acceleration the VBSME in HEVC encoder based on multi- core CPU plus many-core GPU platform. Firstly, a two- stage ME strategy is proposed for dividing ME task onto the CPU and the GPU. Then, a span-wavefront VBSME sequence is designed for efficient synchronization between the threads on the CPU and the threads on the GPU. Experimental results show that the speed of the HEVC encoder with the proposed strategies reaches about 28 fps for 1080P videos with a little compression performance degradation.
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