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Wave field synthesis for 3D audio: architectural prospectives

Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, Georgi Kuzmanov
Computer Engineering Laboratory, Electrical Engineering Dept., Delft University of Technology, Postbus 5031, 2600 GA, Delft, The Netherlands
Proceedings of the 6th ACM conference on Computing frontiers, CF ’09

@conference{theodoropoulos2009wave,

   title={Wave field synthesis for 3D audio: architectural prospectives},

   author={Theodoropoulos, D. and Ciobanu, C.B. and Kuzmanov, G.},

   booktitle={Proceedings of the 6th ACM conference on Computing frontiers},

   pages={127–136},

   year={2009},

   organization={ACM}

}

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In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GPP), a Graphics Processor Unit (GPU) and a Field Programmable Gate Array (FPGA). Previous related work reveals that, up to now, WFS sound systems are based on standard PCs. However, on one hand, contemporary GPUs consist of many multiprocessors that can process data concurrently. On the other hand, recent FPGAs provide huge level of parallelism, and reasonably high performance potentials, which can be exploited very efficiently by smart designers. Furthermore, new parallel programming environments, such as the Compute Unified Device Architecture (CUDA) from NVidia and the Stream from ATI, give to the researchers full access to the GPU resources. We use the CUDA to map the WFS kernel on a GeForce 8600GT GPU. Additionally, we implement a reconfigurable and scalable hardware accelerator for the same kernel, and map it onto Virtex4 FPGAs. We compare both architectural approaches against a baseline GPP implementation on a Pentium D at 3.4 GHz. Our conclusion is that in highly demanding WFS-based audio systems, a low-cost GeForce 8600GT desktop GPU can achieve a speedup of up to 8x comparing to a modern Pentium D implementation. An FPGA-based WFS hardware accelerator consisting of a single rendering unit (RU), can provide a speedup of up 10x comparing to the Pentium D approach. It can fit into small FPGAs and consumes approximately 3 Watts. Furthermore, cascading multiple RUs into a larger FPGA, can boost processing throughput up to more than two orders of magnitude higher than a GPP-based implementation and an order of magnitude better than a low-cost GPU one.
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