2707

3D GPU Architecture using Cache Stacking: Performance, Cost, Power and Thermal analysis

Ahmed Al Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan and Yuan Xie
Department of Computer Science and Engineering, Penn State University
IEEE International Conference on Computer Design, 2009. ICCD 2009, p.254-259
@conference{al20103d,

   title={3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis},

   author={Al Maashri, A. and Sun, G. and Dong, X. and Narayanan, V. and Xie, Y.},

   booktitle={Computer Design, 2009. ICCD 2009. IEEE International Conference on},

   pages={254–259},

   issn={1063-6404},

   year={2010},

   organization={IEEE}

}

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Graphics Processing Units (GPUs) offer tremendous computational and processing power. The architecture requires high communication bandwidth and lower latency between computation units and caches. 3D die-stacking technology is a promising approach to meet such requirements. To the best of our knowledge no other study has investigated the implementation of 3D technology in GPUs. In this paper, we study the impact of stacking caches using the 3D technology on GPU performance. We also investigate the benefits of using 3D stacked MRAM on GPUs. Our work includes cost, power, and thermal analysis of the proposed architectural designs. Our results show a 53% geometric mean performance speedup for iso-cycle time architectures and about 19% for iso-cost architectures.
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