Parallel AES Encryption Engines for Many-Core Processor Arrays

Bin Liu, Bevan M. Baas
Department of Electrical and Computer Engineering, University of California, Davis, CA, 95616, USA
IEEE computer Society Digital Library, preprint, 2011
@article{liu2011parallel,

   title={Parallel AES Encryption Engines for Many-Core Processor Arrays},

   author={Liu, B. and Baas, B.M.},

   journal={IEEE Transactions on Computers},

   volume={1},

   year={2011}

}

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By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an Advanced Encryption Standard (AES) encipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only 6 cores for offline key expansion and 8 cores for online key expansion, while the largest requires 107 cores and 137 cores, respectively. The throughput of each design is examined by both synchronous dataflow models and measurements from a fabricated chip. In comparison with published AES encipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per area and 8.2-18.1 times higher energy efficiency. Moreover, the design shows 2.0 times higher throughput than the TI DSP C6201, and 3.3 times higher throughput per area and 2.9 times higher energy efficiency than the GeForce 8800 GTX.
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