A Compile-Time Managed Multi-Level Register File Hierarchy
The University of Texas at Austin, Austin, TX
The 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2011), 2011
@article{gebhart2011compile,
title={A Compile-Time Managed Multi-Level Register File Hierarchy},
author={Gebhart, M. and Keckler, S.W. and Dally, W.J.},
year={2011}
}
As processors increasingly become power limited, performance improvements will be achieved by rearchitecting systems with energy efficiency as the primary design constraint. While some of these optimizations will be hardware based, combined hardware and software techniques likely will be the most productive. This work redesigns the register file system of a modern throughput processor with a combined hardware and software solution that reduces register file energy without harming system performance. Throughput processors utilize a large number of threads to tolerate latency, requiring a large, energy-intensive register file to store thread context. Our results show that a compiler controlled register file hierarchy can reduce register file energy by up to 54%, compared to a hardware only caching approach that reduces register file energy by 34%. We explore register allocation algorithms that are specifically targeted to improve energy efficiency by sharing temporary register file resources across concurrently running threads and conduct a detailed limit study on the further potential to optimize operand delivery for throughput processors. Our efficiency gains represent a direct performance gain for power limited systems, such as GPUs.
January 19, 2012 by hgpu
