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All-pairs shortest-paths for large graphs on the GPU

Gary J. Katz, Joseph T. Kider

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Tags: CUDA, Graph theory, Mathematics, nVidia, nVidia Quadro FX 5600

October 28, 2010 by hgpu

PSST: A Tutorial for Parallelised Scalable Simulations in TensorFlow

Parallel scalable simulations of biological neural networks using TensorFlow: A beginner’s guide

MUSE: Miami University Simulation Environment

Temporospatial Epidemic Simulations Using Heterogeneous Computing

Pressure Point Analysis framework

Diagnosing Performance Bottlenecks in HPC Applications

Dynamic Distribution Pruning for Efficient Network Architecture Search

Dynamic Distribution Pruning for Efficient Network Architecture Search

Tinker-HP: High Performance Massively Parallel Evolution of Tinker

Raising the Performance of the Tinker-HP Molecular Modeling Package on Intel’s HPC Architectures: a Living Review [Article v1.0]

PyVisc

Classify QCD phase transition with deep learning

Bytespresso: a library for Java to C/CUDA translator based on deep reification

A Development Platform for Embedded Domain-Specific Languages

faimGraph

Breadth-First Search using Dynamic Parallelism on the GPU

Vulkan Multi-GPU application

Multi-GPU Rendering with Vulkan API

Benchmarking Analysis of Vision Kernels on Embedded CPU, GPU and FPGA

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels

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2019

May

13-15

Boston, USA

7th International Workshop on OpenCL, 2019

2019

May

13

Boston, MA, USA

Distributed Heterogeneous Programming in C/C++ (DHPCC++), 2019

2019

May

14

Larnaca, Cyprus

3rd International Workshop on Theoretical Approaches to Performance Evaluation, Modeling and Simulation (TAPEMS), 2019

2019

July

26-28

Rome, Italy

International Conference on Frontiers of Neural Networks (ICFNN), 2019

2019

July

26-28

Rome, Italy

International Conference on Frontiers of Artificial Intelligence and Machine Learning (FAIML), 2019

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