GPGPU Multi Object Bayesian Tracking with an embedded System on a Chip
School of Information Technology and Mathematical Sciences, Division of Information Technology, Engineering and the Environment, University of South Australia
University of South Australia, 2015
@article{webb2015gpgpu,
title={GPGPU Multi Object Bayesian Tracking with an embedded System on a Chip},
author={Webb, David},
year={2015}
}
Current embedded multi object tracking system implementations are dominated by the use of Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) as application accelerators. These offer many of the traits desirable for embedded and real time systems, including; task oriented architectures, deterministic latency and low power requirements. The drawbacks to these approaches are the difficulty of development and the high costs associated with prototyping and developing systems and hardware. Other embedded approaches feature simplified algorithms which are not robust for multiple types of targets or complex scenes. Modern embedded system on a chip (SoC) platforms offer GPUs that are now capable of general purpose computing, enabling the efficient acceleration of parallel problems. This study focuses on multi-object trackers that are capable of tracking targets without the need for target specific customisation. Such trackers usually require computation resources that are unavailable on embedded platforms. The use of full sized computers is not viable for mobile applications which have constraints on available power and heat dissipation. This thesis presents what is believed to be the first GPU accelerated embedded SoC based implementation of a complex Bayesian multi-object tracker. The thesis explores the applicability and optimal usage of CPU and GPGPU techniques for the tracker on both SoC and Desktop platforms. The presented SoC based implementation is a heterogeneous design, with a hybrid CPU and GPU based processing path. This implementation capable of real time tracking of four targets at 21.5 frames per second. The SoC implementation is five times more power efficient when compared with an existing FPGA accelerated CPU based implementation. It is 85% more power efficient than the same version implemented on a desktop CPU and discrete GPU. The desktop GPU accelerated implementation provides the highest throughput version of the CACTuS multi-target tracker to date. The research has shown that a SoC based platform, using the GPU and CPU implementation of the tracker is more power efficient on a frames per second per Watt basis than using the CPU alone.
February 2, 2016 by hgpu
