Algorithmic Trading: A brief, computational finance case study on data centre FPGAs

Gordon Inggs
Circuit and Systems Research Group, Department of Electrical and Electronic Engineering, Imperial College London
arXiv:1607.05069 [cs.DC], (10 Jan 2016)


   title={Algorithmic Trading: A brief, computational finance case study on data centre FPGAs},

   author={Inggs, Gordon},






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Increasingly FPGAs will be deployed at scale due to the need for increased need for power efficient computation and improved high level synthesis tool flows, creating a new category of device: data centre FPGAs. A method for using these FPGAs is to identify what proportion of a given workload would benefit from being implemented upon the available FPGAs while minimising communication off-chip. As part of the implementation of these tasks, care should be taken in identifying the parallel execution mode, task or pipeline parallelism that should be used. When considering a case study of computational finance tasks, a benchmark workload of Heston and Black-Scholes-based options implemented using OpenCL and OpenSPL, the benefit of this method of using data centre FPGAs is illustrated. These devices deliver latency performance close to that of workstation grade GPUs, while requiring considerably less energy, resulting in 30% more floating point operations per Joule of energy consumed.
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