Batched Shift Reduce Parsing with Lists of Vectors on CUDA

Andrew Drozdov
New York University
New York University, 2016


   title={Batched Shift Reduce Parsing with Lists of Vectors on CUDA},

   author={Drozdov, Andrew},



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Shift Reduce Parsing is a common algorithm used in compilers and natural language processing, and can be used to compose a sequence of fixed-length vectors into a single vector of equal length. Previous versions are implemented using predetermined computational graphs that trade excessive memory and computation to minimize transfers of memory from the device to the host. In this paper, I present a version of Shift Reduce Parsing that uses only the necessary memory and computation, show that the memory transfer is insignificant when implemented properly, and analyze how the sequence of transitions can effect computation when running a batched version of this algorithm, as is common in deep learning programs.
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