Barra: A Parallel Functional Simulator for GPGPU
ELIAUS-PROMES (UPVD), Perpignan, FRANCE
18th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 2010
@conference{collange2010barra,
title={Barra: A Parallel Functional Simulator for GPGPU},
author={Collange, S. and Daumas, M. and Defour, D. and Parello, D.},
booktitle={2010 18th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems},
pages={351–360},
issn={1526-7539},
year={2010},
organization={IEEE}
}
We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the native instruction set of the Tesla architecture at the functional level. The inputs are CUDA executables produced by NVIDIA tools. No alterations are needed to perform simulations. As it uses parallelism, Barra generates detailed statistics on executions in about the time needed by CUDA to operate in emulation mode. We use it to understand and explore the micro-architecture design spaces of GPUs.
January 15, 2011 by hgpu
