Frame-based parallelization of MPEG-4 on compute unified device architecture (CUDA)
Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, India
IEEE 2nd International Advance Computing Conference (IACC), 2010, p.267-272
@conference{ailawadi2010frame,
title={Frame-based parallelization of MPEG-4 on compute unified device architecture (CUDA)},
author={Ailawadi, D. and Mohapatra, M.K. and Mittal, A.},
booktitle={Advance Computing Conference (IACC), 2010 IEEE 2nd International},
pages={267–272},
year={2010},
organization={IEEE}
}
Due to its object based nature, flexible features and provision for user interaction, MPEG-4 encoder is highly suitable for parallelization. The most critical and time-consuming operation of encoder is motion estimation. Nvidia’s general-purpose graphical processing unit (GPGPU) architecture allows for a massively parallel stream processor model at a very cheap price (in a few thousands Rupees). However synchronization of parallel calculations and repeated device to host data transfer is a major challenge in parallelizing motion estimation on CUDA. Our solution employs optimized and balanced parallelization of motion estimation on CUDA. This paper discusses about frame-based parallelization wherein parallelization is done at two levels – at macroblock level and at search range level. We propose a further division of macroblock to optimize parallelization. Our algorithm supports real-time processing and streaming for key applications such as e-learning, telemedicine and video-surveillance systems, as demonstrated by experimental results.
March 8, 2011 by hgpu
