Scalable instruction set simulator for thousand-core architectures running on GPGPUs
ESL, EPFL, Lausanne, Switzerland
International Conference on High Performance Computing and Simulation (HPCS), 2010
@conference{raghav2010scalable,
title={Scalable instruction set simulator for thousand-core architectures running on GPGPUs},
author={Raghav, S. and Ruggiero, M. and Atienza, D. and Pinto, C. and Marongiu, A. and Benini, L.},
booktitle={High Performance Computing and Simulation (HPCS), 2010 International Conference on},
pages={459–466},
year={2010},
organization={IEEE}
}
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.
April 9, 2011 by hgpu
