Efficient parallelized particle filter design on CUDA
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei City 10617, Taiwan
IEEE Workshop on Signal Processing Systems (SIPS), 2010
@conference{chao2010efficient,
title={Efficient parallelized particle filter design on CUDA},
author={Chao, M.A. and Chu, C.Y. and Chao, C.H. and Wu, A.Y.},
booktitle={Signal Processing Systems (SIPS), 2010 IEEE Workshop on},
pages={299–304},
issn={1520-6130},
organization={IEEE}
}
Particle filtering is widely used in numerous nonlinear applications which require reconfigurability, fast prototyping, and online parallel signal processing. The emerging computing platform, CUDA, may be regarded as the most appealing platform for such implementation. However, there are not yet literatures exploring how to utilize CUDA for particle filters. This parer aims to provide two design techniques, A) finite-redraw importance-maximizing (FRIM) prior editing and B) localized resampling, for efficient implementation of particle filters on CUDA, which can be verified to reduce global operations and provide significant speedup. The modifications on algorithm and architectural mapping are evaluated with conceptual and quantitative analysis. From the classic bearings-only tracking experiments, the proposed design is 5.73 times faster than the direct implementation on GeForce 9400m.
April 13, 2011 by hgpu
