Exploring scalability of FIR filter realizations on Graphics Processing Units
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
IEEE International Conference on Electro/Information Technology (EIT), 2010
@conference{rebacz2010exploring,
title={Exploring scalability of FIR filter realizations on Graphics Processing Units},
author={Rebacz, J. and Oruklu, E. and Saniie, J.},
booktitle={Electro/Information Technology (EIT), 2010 IEEE International Conference on},
pages={1–5},
issn={2154-0357},
organization={IEEE}
}
General-Purpose Computing on Graphics Processing Units (GPGPU) has lately been of great interest due to the release of architectures and software that simplifies programming graphics cards. This study explores how performance scales with FIR digital filters by varying the number of taps and the samples. We also discuss the trade-offs with various techniques for GPGPU programming in CUDA.
April 20, 2011 by hgpu
