Design of a parallel AES for graphics hardware using the CUDA framework
Politecnico di Milano, Italy
IEEE International Symposium on Parallel & Distributed Processing, 2009, IPDPS 2009, pp.1-8
@article{di2009design,
title={Design of a parallel AES for graphics hardware using the CUDA framework},
author={Di Biagio, A. and Barenghi, A. and Agosta, G. and Pelosi, G.},
year={2009},
publisher={IEEE}
}
Web servers often need to manage encrypted transfers of data. The encryption activity is computationally intensive, and exposes a significant degree of parallelism. At the same time, cheap multicore processors are readily available on graphics hardware, and toolchains for development of general purpose programs are being released by the vendors. In this paper, we propose an effective implementation of the AES-CTR symmetric cryptographic primitive using the CUDA framework. We provide quantitative data for different implementation choices and compare them with the common CPU-based OpenSSL implementation on a performance-cost basis. With respect to previous works, we focus on optimizing the implementation for practical application scenarios, and we provide a throughput improvement of over 14 times. We also provide insights on the programming knowledge required to efficiently exploit the hardware resources by exposing the different kinds of parallelism built in the AES-CTR cryptographic primitive.
July 5, 2011 by hgpu
