Fast circuit simulation on graphics processing units

Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry
Department of ECE, Texas A&M University, College Station, TX
Asia and South Pacific Design Automation Conference, 2009. ASP-DAC 2009


   title={Fast circuit simulation on graphics processing units},

   author={Gulati, K. and Croix, J.F. and Khatr, S.P. and Shastry, R.},

   booktitle={Proceedings of the 2009 Asia and South Pacific Design Automation Conference},



   organization={IEEE Press}


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SPICE based circuit simulation is a traditional workhorse in the VLSI design process. Given the pivotal role of SPICE in the IC design flow, there has been significant interest in accelerating SPICE. Since a large fraction (on average 75%) of the SPICE runtime is spent in evaluating transistor model equations, a significant speedup can be availed if these evaluations are accelerated. This paper reports on our early efforts to accelerate transistor model evaluations using a Graphics Processing Unit (GPU). We have integrated this accelerator with a commercial fast SPICE tool. Our experiments demonstrate that significant speedups (2.36times on average) can be obtained. The asymptotic speedup that can be obtained is about 4times. We demonstrate that with circuits consisting of as few as about 1000 transistors, speedups in the neighborhood of this asymptotic value can be obtained. By utilizing the recently announced (but not currently available) quad GPU systems, this speedup could be enhanced further, especially for larger designs.
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