Identifying scalar behavior in CUDA kernels
ARENAIRE (Inria Grenoble Rhone-Alpes / LIP Laboratoire de l’Informatique du Parallelisme), INRIA – CNRS : UMR5668 – Universite Claude Bernard – Lyon I – Ecole Normale Superieure de Lyon
Technical report hal-00555134, 2011
@article{collange2011identifying,
title={Identifying scalar behavior in CUDA kernels},
author={Collange, S.},
year={2011}
}
We propose a compiler analysis pass for programs expressed in the Single Program, Multiple Data (SPMD) programming model. It identifies statically several kinds of regular patterns that can occur between adjacent threads, including common computations, memory accesses at consecutive locations or at the same location and uniform control flow. This knowledge can be exploited by SPMD compilers targeting SIMD architectures. We present a compiler pass developed within the Ocelot framework that performs this analysis on NVIDIA CUDA programs at the PTX intermediate language level. Results are compared with optima obtained by simulation of several sets of CUDA benchmarks.
September 26, 2011 by hgpu
