high performance computing on graphics processing units: hgpu.org

The SIMD (Single Instruction-Multiple Data) execution model of Graphics Processing Units (GPUs) allows for many concurrent threads to simultaneously request data from the memory subsystem. This imposes a large bandwidth demand on the memory interfaces at each level. Each level of the memory hierarchy needs to provide enough bandwidth in order to ensure good response time to the cores. In particular, the GDDR (particularly GDDR5 as in current GPGPU systems) memory controllers at the on-chip/off-chip boundary become critical, since these are the primary memory interface between the GPGPU and the GDDR memory. These are crucial to efficiently manage the off-chip memory accesses. One important aspect of the access management is the scheduling of memory requests, which can leverage the locality characteristics of the applications to increase throughput. In this work, a survey is presented that explores some of the stateof-the-art off-chip memory access scheduling mechanisms implemented in GPGPUs. Results are presented for each of the mechanisms referenced, showing the impact on the performance of the architectures when running different benchmarks. Moreover, state-of-the-art research now seeks to integrate both CPU and GPGPUs on the same die, implying the sharing of memory resources between both systems. As we shall see, this makes the scheduling problem even more complex, therefore creating a necessity of scheduling mechanisms tailored for these cases.