high performance computing on graphics processing units: hgpu.org

With the commissioning of the Insertable B-Layer (IBL) in 2013 at the ATLAS experiment 12~million additional pixels will be added to the current Pixel Detector. While the idea of employing pairs of VME based Read-Out Driver (ROD) and Back of Crate (BOC) cards in the read-out chain remains unchanged, modifications regarding the IBL calibration procedure were introduced to overcome current hardware limitations. The analysis of calibration histograms will no longer be performed on the RODs, but on an external computing farm that is connected to the RODs via Ethernet. This thesis contributes to the new IBL calibration procedure and presents a concept for a scalable software and hardware architecture. An embedded system targeted to the ROD FPGAs is realized for sending data from the RODs to the fit farm servers and benchmarks are carried out with a Linux based networking stack, as well as a standalone software stack. Furthermore, the histogram fitting algorithm currently being employed on the Pixel Detector RODs is ported to a GPU architecture and optimized for parallel execution, increasing the performance of a previous implementation by a factor of~10. As an alternative, CPU based fitting methods are investigated for their practicability.