Composing multiple StarPU applications over heterogeneous machines: a supervised approach

A.-E Hugo A. Guermouche P.-A. Wacrenier R. Namyst
INRIA, LaBRI, University of Bordeaux, Talence, France
hal-00824514, (21 May 2013)




   title={Composing multiple StarPU applications over heterogeneous machines: a supervised approach},

   author={Hugo, Andra-Ecaterina and Guermouche, Abdou and Namyst, Raymond and Wacrenier, Pierre-Andr{‘e}},


   affiliation={RUNTIME – INRIA Bordeaux – Sud-Ouest , Laboratoire Bordelais de Recherche en Informatique – LaBRI , HiePACS – INRIA Bordeaux – Sud-Ouest},

   booktitle={Third International Workshop on Accelerators and Hybrid Exascale Systems},

   address={Boston, {‘E}tats-Unis},






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Enabling HPC applications to perform efficiently when invoking multiple parallel libraries simultaneously is a great challenge. Even if a single runtime system is used underneath, scheduling tasks or threads coming from different libraries over the same set of hardware resources introduces many issues, such as resource oversubscription, undesirable cache flushes or memory bus contention. This paper presents an extension of StarPU, a runtime system specifically designed for heterogeneous architectures, that allows multiple parallel codes to run concurrently with minimal interference. Such parallel codes run within scheduling contexts that provide confined execution environments which can be used to partition computing resources. Scheduling contexts can be dynamically resized to optimize the allocation of computing resources among concurrently running libraries. We introduce a hypervisor that automatically expands or shrinks contexts using feedback from the runtime system (e.g. resource utilization). We demonstrate the relevance of our approach using benchmarks invoking multiple high performance linear algebra kernels simultaneously on top of heterogeneous multicore machines. We show that our mechanism can dramatically improve the overall application run time (-34%), most notably by reducing the average cache miss ratio (-50%).
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