Architecture | Page 2

Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan

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Tags: 3D Graphics and Realism, Architecture, Computer science, Hardware, Larrabee

December 10, 2010 by hgpu

Shader-based tessellation to save memory bandwidth in a mobile multimedia processor

Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim

Tags: Architecture, Computer science, Hardware, Memory, Tessellation

November 28, 2010 by hgpu

Complexity effective memory access scheduling for many-core accelerator architectures

George L. Yuan, Ali Bakhoda, Tor M. Aamodt

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Tags: Architecture, Computer science, CUDA, Hardware, Memory, nVidia

November 28, 2010 by hgpu

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

SimSYCL: A SYCL Implementation Targeting Development, Debugging, Simulation and Conformance

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

94% on CIFAR-10 in 3.29 Seconds on a Single GPU

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

See all packages

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high performance computing on graphics processing units: hgpu.org

Toward a multicore architecture for real-time ray-tracing

Merge: a programming model for heterogeneous multi-core systems

Larrabee: a many-core x86 architecture for visual computing

Shader-based tessellation to save memory bandwidth in a mobile multimedia processor

Complexity effective memory access scheduling for many-core accelerator architectures

Recent source codes

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

GPU plugin for PySCF

QArray

Celerity: High-level C++ for Accelerator Clusters