high performance computing on graphics processing units: hgpu.org

hgpu.org » Intel B70

Stencil Computation at the Intersection of AI and HPC

Timothee Ewart, Mauricio Araya-Polo

View

Tags: AI, AMD, AMD Radeon Instinct MI325X, Computer science, HPC, Intel Arc B580, Intel B70, Intel Data Center GPU Max 1550, nVidia, nVidia A100, nVidia H100, nVidia RTX PRO 6000, performance portability, Stencil computation, SYCL, Triton

September 14, 2026 by hgpu

Qwen3-235B @ 1M tokens on AMD MI355X

CHUNDER: Enabling Million-Token Qwen3 Serving on AMD ROCm

CUDA++ for the NVIDIA DGX Spark

Reverse Engineering the CUDA Software Stack: A Clean-Room GPU Machine-Code Toolchain for the NVIDIA GB10

ATTUNE: Agentic Throughput Tuning for LLM Training

ATTUNE: Agentic Throughput Tuning for LLM Training

HPCAgent-Bench: A Framework for Sound Benchmarking of Code-Optimizing Agents, Harnesses, and Skills

HPCAgent-Bench: A Framework for Sound Benchmarking of Code-Optimizing Agents, Harnesses, and Skills

Brian2 Atlas

A Unified Intermediate Representation and Execution Architecture for Heterogeneous and Distributed Neural Simulation

AgentGarten: Code Worlds for Evolving Agents

AgentGarten: Code Worlds for Evolving Agents

KernelLens: Automated Triton-to-C++ Compiler for Enterprise Inference Runtimes

KernelLens: Deploying Triton Kernels to C++ Inference Engines

KernelZero: Co-Evolving Proposer and Coder for Continuously Improved GPU Kernel Generation

KernelZero: Co-Evolving Proposer and Coder for Continuously Improved GPU Kernel Generation

Introduction to Computer Vision

Introduction to Computer Vision

ACT: Accelerator Compiler Toolkit

Automatically Generating ML Compiler Backends from Tensor Accelerator ISA Descriptions

See all packages

* * *

* * *

HGPU group © 2010-2026 hgpu.org

All rights belong to the respective authors

Login | Sitemap | Feedback | Policy

Contact us: