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A Survey of Cache Partitioning Techniques for Multicore Processors

Sparsh Mittal

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Tags: cache partitioning, computer architecture, Multicore processors, Power management, shared cache

March 10, 2017 by sparsh0mittal

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tntorch - Tensor Network Learning with PyTorch

tntorch: Tensor Network Learning with PyTorch

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark

MapReduce for Counting Word Frequencies with MPI and GPUs

MapReduce for Counting Word Frequencies with MPI and GPUs

CoDL: Efficient CPU-GPU Co-execution for Deep Learning Inference on Mobile Devices

CoDL: Efficient CPU-GPU Co-execution for Deep Learning Inference on Mobile Devices

SYCLCOMP Utilities

On the Compilation Performance of Current SYCL Implementations

M1 GPUs for (scientific) computations in C++

Seamless GPU acceleration for C++ based physics with the Metal Shading Language on Apple’s M series unified chips

CUB: Cooperative primitives for CUDA C++

Onesweep: A Faster Least Significant Digit Radix Sort for GPUs

Simulator and workload generator for Edge-to-Cloud environments

FELARE: Fair Scheduling of Machine Learning Applications on Heterogeneous Edge Systems

piet-gpu: An experimental GPU compute-centric 2D renderer

Fast GPU bounding boxes on tree-structured scenes

Large-scale Self-supervised Pre-training Across Tasks, Languages, and Modalities

Lossless Acceleration for Seq2seq Generation with Aggressive Decoding

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