11905

Parallel Circuit Simulation on Graphical Processing Unit

Aram Baghdasaryan
Synopsys Armenia CJSC, State Engineering University of Armenia, Yerevan, Armenia
Small System Simulation Symposium (SSSS’14), 2014
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So high integration of IC design and mix VLSI design have brought new complexity in IC design. This complexity brings new challenges for simulation IC time. There is interest to speed up Spice [1] simulation because for large IC simulation can take several days. Average 75% percent of simulation time is spent in evaluating transistor model equations. This report is discussing accelerating transistor model evaluation using Graphical Processing Unit (GPU). For speed up simulation time also used scheduling algorithms which help schedule tasks according to running time criteria. According to results method which is represented in this paper sped up simulation to 2.5 times.
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