TTC: A Tensor Transposition Compiler for Multiple Architectures
AICES, RWTH Aachen University, Germany
arXiv:1607.01249 [cs.MS], (5 Jul 2016)
@article{springer2016tensor,
title={TTC: A Tensor Transposition Compiler for Multiple Architectures},
author={Springer, Paul and Sankaran, Aravind and Bientinesi, Paolo},
year={2016},
month={jul},
archivePrefix={"arXiv"},
primaryClass={cs.MS},
doi={10.1145/2935323.2935328}
}
We consider the problem of transposing tensors of arbitrary dimension and describe TTC, an open source domain-specific parallel compiler. TTC generates optimized parallel C++/CUDA C code that achieves a significant fraction of the system’s peak memory bandwidth. TTC exhibits high performance across multiple architectures, including modern AVX-based systems (e.g.,~Intel Haswell, AMD Steamroller), Intel’s Knights Corner as well as different CUDA-based GPUs such as NVIDIA’s Kepler and Maxwell architectures. We report speedups of TTC over a meaningful baseline implementation generated by external C++ compilers; the results suggest that a domain-specific compiler can outperform its general purpose counterpart significantly: For instance, comparing with Intel’s latest C++ compiler on the Haswell and Knights Corner architecture, TTC yields speedups of up to $8times$ and $32times$, respectively. We also showcase TTC’s support for multiple leading dimensions, making it a suitable candidate for the generation of performance-critical packing functions that are at the core of the ubiquitous BLAS 3 routines.
July 8, 2016 by hgpu
