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TTC: A Tensor Transposition Compiler for Multiple Architectures

Paul Springer, Aravind Sankaran, Paolo Bientinesi

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Tags: BLAS, Compilers, Computer science, CUDA, Intel Xeon Phi, Linear Algebra, Mathematical Software, nVidia, nVidia GeForce 840 M, Package, Performance, Tesla K40

July 8, 2016 by hgpu

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Rodinia Benchmarks for DPC++

Evaluation of Intel’s DPC++ Compatibility Tool in heterogeneous computing

DCA++: a state of the art implementation of the dynamical cluster approximation

Optimizing the Performance of Parallel and Concurrent Applications Based on Asynchronous Many-Task Runtimes

tntorch - Tensor Network Learning with PyTorch

tntorch: Tensor Network Learning with PyTorch

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark

MapReduce for Counting Word Frequencies with MPI and GPUs

MapReduce for Counting Word Frequencies with MPI and GPUs

CoDL: Efficient CPU-GPU Co-execution for Deep Learning Inference on Mobile Devices

CoDL: Efficient CPU-GPU Co-execution for Deep Learning Inference on Mobile Devices

SYCLCOMP Utilities

On the Compilation Performance of Current SYCL Implementations

M1 GPUs for (scientific) computations in C++

Seamless GPU acceleration for C++ based physics with the Metal Shading Language on Apple’s M series unified chips

CUB: Cooperative primitives for CUDA C++

Onesweep: A Faster Least Significant Digit Radix Sort for GPUs

Simulator and workload generator for Edge-to-Cloud environments

FELARE: Fair Scheduling of Machine Learning Applications on Heterogeneous Edge Systems

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