high performance computing on graphics processing units: hgpu.org

Programmers usually rely on one from a set of optimizing compiler optimization level flags shipped with the compiler they are using to compile their source code. Those compiler flags represent fixed compiler pass sequences, and therefore in some situations better performance and/or other metrics such as code size can be achieved if using compiler sequences "tuned" for the specific source code and target architecture. In order to maximize the potential of optimization made available with compiler sequence exploration, it is required not only to select what compiler passes to execute, but also to select their order of execution. With the growing number of analysis and transformation compiler passes that are becoming available on modern compilers, the selection of compiler sequences can be a challenge, as the exploration space quickly becomes too large, thus requiring the use of optimization algorithms suited to the task of finding close to optimum compiler sequences and/or heuristics to prune the exploration space. In this thesis we propose a modular system that is capable of exploring compiler pass sequences. The system relies on LARA, an aspect oriented programming language, to implement Design Space Exploration (DSE) algorithms/methods for exploring compiler sequences, and additionally, in the case of one of the compiler toolchains supported by this system, LARA can be used to internally guide the actions of the compiler tools in relation to where to apply specific transformations in the program/application being optimized. We present DSE schemes that we researched and developed in the context of this work. In the experiments presented in this thesis we mainly targeted processors and benchmarks related with embedded systems. Using our approaches, we were able to efficiently and consistently achieve significant optimization improvements versus any the standard optimization levels available in current compilers.