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Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking

Zhe Jia, Marco Maggioni, Benjamin Staiger, Daniele P. Scarpazza
High Performance Computing R&D Team, Citadel, 131 S. Dearborn St., Chicago
arXiv:1804.06826 [cs.DC], (18 Apr 2018)

@article{jia2018dissecting,

   title={Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking},

   author={Jia, Zhe and Maggioni, Marco and Staiger, Benjamin and Scarpazza, Daniele P.},

   year={2018},

   month={apr},

   archivePrefix={"arXiv"},

   primaryClass={cs.DC}

}

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Every year, novel NVIDIA GPU designs are introduced. This rapid architectural and technological progression, coupled with a reluctance by manufacturers to disclose low-level details, makes it difficult for even the most proficient GPU software designers to remain up-to-date with the technological advances at a microarchitectural level. To address this dearth of public, microarchitectural-level information on the novel NVIDIA GPUs, independent researchers have resorted to microbenchmarks-based dissection and discovery. This has led to a prolific line of publications that shed light on instruction encoding, and memory hierarchy’s geometry and features at each level. Namely, research that describes the performance and behavior of the Kepler, Maxwell and Pascal architectures. In this technical report, we continue this line of research by presenting the microarchitectural details of the NVIDIA Volta architecture, discovered through microbenchmarks and instruction set disassembly. Additionally, we compare quantitatively our Volta findings against its predecessors, Kepler, Maxwell and Pascal.
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