Instructions’ Latencies Characterization for NVIDIA GPGPUs

Yehia Arafa, Abdel-Hameed Badawy, Gopinath Chennupati, Nandakishore Santhi, Stephan Eidenbenz
Klipsch School of ECE, New Mexico State University. Las Cruces, NM 88003, USA
arXiv:1905.08778 [cs.DC], (21 May 2019)


   title={TInstructions’ Latencies Characterization for NVIDIA GPGPUs},

   author={Arafa, Yehia and Badawy, Abdel-Hameed and Chennupati, Gopinath and Santhi, Nandakishore and Eidenbenz, Stephan},






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The last decade has seen a shift in the computer systems industry where heterogeneous computing has become prevalent. Nowadays, Graphics Processing Units (GPUs) are in a variety of systems from supercomputers to mobile phones and tablets. They are not only used for graphics operations but rather as general-purpose special hardware (GPGPUs) to boost the performance of compute-intensive applications. However, the percentage of undisclosed characteristics beyond what vendors provide is small. In this paper, we propose a very low overhead and portable analysis for exposing the hidden latency of each individual instruction executing in the pipeline and different access latencies of the various memory hierarchies at the microarchitecture level. We also show the impact of the possible optimizations a CUDA compiler have over the various latencies. We run our evaluation on seven different high-end NVIDIA GPUs from five different generations/architectures namely: Kepler, Maxwell, Pascal, Volta, and Turing. We believe that this work would help architects have an accurate characterization of the latencies of these GPUs, which would subsequently help in modeling the hardware accurately. In addition, this would also make application developers more aware of how to optimize their applications.
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