Efficient fault simulation on many-core processors
Institut fuer Technische Informatik, Universitaet Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany
47th ACM/IEEE Design Automation Conference (DAC), 2010, p.380-385
@conference{kochte2010efficient,
title={Efficient fault simulation on many-core processors},
author={Kochte, M.A. and Schaal, M. and Wunderlich, H.J. and Zoellin, C.G.},
booktitle={Design Automation Conference (DAC), 2010 47th ACM/IEEE},
pages={380–385},
issn={0738-100X},
year={2010},
organization={IEEE}
}
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structures are particularly computationally expensive as a large number of patterns has to be evaluated. In this work, we propose to map a fault simulation algorithm based on the parallel-pattern single-fault propagation (PPSFP) paradigm to many-core architectures and describe the involved algorithmic optimizations. Many-core architectures are characterized by a high number of simple execution units with small local memory. The proposed fault simulation algorithm exploits the parallelism of these architectures by use of parallel data structures. The algorithm is implemented for the NVIDIA GT200 Graphics Processing Unit (GPU) architecture and achieves a speed-up of up to 17x compared to an existing GPU fault-simulation algorithm and up to 16x compared to state-of-the-art algorithms on conventional processor architectures.
January 13, 2011 by hgpu
