Many-core parallel computing – Can compilers and tools do the heavy lifting?

W.-m.W. Hwu
FCRP GSRC, Illinois UPCRC, Illinois CUDA CoE, IACAT, IMPACT, University of Illinois, Urbana-Champaign, Urbana, IL, USA
IEEE International Symposium on Parallel & Distributed Processing, 2009. IPDPS 2009


   title={Many-core parallel computing-Can compilers and tools do the heavy lifting?},

   author={Wen-mei, W.H.},




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Modern GPUs such as the NVIDIA GeForce GTX280, ATI Radeon 4860, and the upcoming Intel Larrabee are massively parallel, many-core processors. Today, application developers for these many-core chips are reporting 10X-100X speedup over sequential code on traditional microprocessors. According to the semiconductor industry roadmap, these processors could scale up to over 1,000X speedup over single cores by the end of the year 2016. Such a dramatic performance difference between parallel and sequential execution will motivate an increasing number of developers to parallelize their applications. Today, an application programmer has to understand the desirable parallel programming idioms, manually work around potential hardware performance pitfalls, and restructure their application design in order to achieve their performance objectives on many-core processors. Although many researchers have given up on parallelizing compilers, I will show evidence that by systematically incorporating high-level application design knowledge into the source code, a new generation of compilers and tools can take over the heavy lifting in developing and tuning parallel applications. I will also discuss roadblocks whose removal will require innovations from the entire research community.
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