Acceleration of Functional Validation Using GPGPU

Lalith Suresh, Navaneeth Rameshan, M. S. Gaur, Mark Zwolinski, Vijay Laxmi
ESD Group, University of Southampton, UK
Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011


   title={Acceleration of Functional Validation using GPGPU},

   author={Suresh, L. and Rameshan, N. and Gaur, MS and Zwolinski, M. and Laxmi, V.},

   booktitle={Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on},





Download Download (PDF)   View View   Source Source   



Logic simulation of a VLSI chip is a computationally intensive process. There exists an urgent need to map functional validation algorithms onto parallel architectures to aid hardware designers in meeting time-to-market constraints. In this paper, we propose three novel methods for logic simulation of combinational circuits on GPGPUs. Initial experiments run on two methods using benchmark circuits using NVIDIA GPGPUs suggest that these methods can be used for accelerating the EDA design flow process.
No votes yet.
Please wait...

* * *

* * *

HGPU group © 2010-2024 hgpu.org

All rights belong to the respective authors

Contact us: