7914

A Performance Model for Memory Bandwidth Constrained Applications on Graphics Engines

Lin Ma, Roger D. Chamberlain
Dept. of Computer Science and Engineering, Washington University in St. Louis
23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2012

@article{ma2012performance,

   title={A Performance Model for Memory Bandwidth Constrained Applications on Graphics Engines},

   author={Ma, L. and Chamberlain, R.D.},

   year={2012}

}

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Graphics engines are excellent execution platforms for high-throughput computations that exploit a large degree of available parallelism. The achieved performance is, however, highly dependent on the access patterns that the application imposes on the memory subsystem. Here, we propose an analytic model that helps improve the understanding of the performance of memory-limited kernels that employ random memory access schemes, especially as impacted by cache and various configuration parameters that can be used to tune kernel execution, such as the number of blocks and the number of threads per block. The analytic model is first explored through the use of a synthetic micro-benchmark, which is then followed by an empirical validation using a pair of production applications used in computational biology.
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