high performance computing on graphics processing units: hgpu.org

hgpu.org » Hardware Architecture

Exploring Microcontrollers in GPUs

Yusuke Fujii, Takuya Azumi, Nobuhiko Nishio, Shinpei Kato

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Tags: Computer science, CUDA, Hardware Architecture, nVidia, nVidia GeForce GTX 480

August 7, 2013 by hgpu

SIMD Divergence Optimization through Intra-Warp Compaction

Aniruddha S. Vaidya, Anahita Shayesteh, Dong Hyuk Woo, Roy Saharoy, Mani Azimi

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Tags: Computer science, Hardware Architecture, OpenCL, OpenGL, Performance

July 12, 2013 by hgpu

Cost-Effective Soft-Error Protection for SRAM-Based Structures in GPGPUs

Jingweijia Tan, Zhi Li, Xin Fu

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Tags: Computer science, CUDA, Energy-efficient computing, Hardware Architecture, nVidia

June 13, 2013 by hgpu

Performance Evaluation of Sparse Matrix Multiplication Kernels on Intel Xeon Phi

Erik Saule, Kamer Kaya, Umit V. Catalyurek

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Tags: Computer science, CUDA, Hardware Architecture, Intel, Intel Phi, Matrix multiplication, nVidia, Performance, Sparse matrix, Tesla C2050, Tesla K20

February 6, 2013 by hgpu

Survey On The Off-Chip Scheduling of Memory Accesses in the Memory Interface Of GPUs

Luis Angel Garrido Platero

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Tags: Computer science, CUDA, GPGPU-sim, Hardware Architecture, Memory, nVidia, Performance

January 31, 2013 by hgpu

GPUDet: A Deterministic GPU Architecture

Hadi Jooybar, Wilson W. L. Fung, Mike O'Connor, Joseph Devietti, Tor M. Aamodt

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Tags: Computer science, GPGPU-sim, Hardware Architecture, nVidia, nVidia GeForce GTX 480

January 29, 2013 by hgpu

Warped Register File: A Power Efficient Register File for GPGPUs

Mohammad Abdel-Majeed, Murali Annavaram

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Tags: Computer science, CUDA, GPGPU-sim, Hardware Architecture, nVidia, Performance

January 28, 2013 by hgpu

GPU Architecture and the Programming Environment

Stanislav Stankovic, Dusan Gajic, Radomir S. Stankovic

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Tags: Computer science, Hardware Architecture, Review

December 10, 2012 by hgpu

Dynamic Warp Resizing in High-Performance SIMT

Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari

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Tags: Computer science, Hardware Architecture, Memory, Performance

August 14, 2012 by hgpu

Investigating Warp Size Impact in GPUs

Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari

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Tags: Computer science, Hardware Architecture

May 23, 2012 by hgpu

Toolchain for programming, simulating and studying the XMT many-core architecture

Fuat Keceli, Alexandros Tzannes, George C. Caragea, Rajeev Barua, Uzi Vishkin

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Source codes

Tags: Algorithms, Compilers, Computer science, Hardware Architecture, nVidia, nVidia GeForce GTX 280, Package

December 24, 2011 by hgpu

The Future in Mobile Multicore Computing

Blake Hurd, Chiu C. Tan, Jie Wu

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Tags: Computer science, Hardware Architecture, Performance

December 20, 2011 by hgpu

Introduction to Computer Vision

KernelZero: Co-Evolving Proposer and Coder for Continuously Improved GPU Kernel Generation

ACT: Accelerator Compiler Toolkit

Automatically Generating ML Compiler Backends from Tensor Accelerator ISA Descriptions

pytest-gpu-proof: A Simple Pytest Extension for Local GPU Code Testing

pytest-gpu-proof: Enabling Cloud-CPU Continuous Integration for GPU Code with Local GPU Attestation

Accelerating the Mitigation of LLM Inference Nondeterminism Across GPU Architectures

nvsass-disassembler

Automated Instruction Encoding Synthesis for Modern GPU ISA Compression

PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving

AutoTuneBench: Trustworthy Measurement for Agent Auto-Tuning of LLM Serving Engines

EinsummableV3 - graph-based computation with tensor operations support

Every Kernel Is a Join: Automatic Multi-GPU Parallelism for AI Computations in Einsummable

MaxKernel: Intelligent TPU Kernel Engineering Agents

MaxKernel: Agentic Kernel Generation for TPUs

See all packages

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high performance computing on graphics processing units: hgpu.org

Exploring Microcontrollers in GPUs

SIMD Divergence Optimization through Intra-Warp Compaction

Cost-Effective Soft-Error Protection for SRAM-Based Structures in GPGPUs

Performance Evaluation of Sparse Matrix Multiplication Kernels on Intel Xeon Phi

Survey On The Off-Chip Scheduling of Memory Accesses in the Memory Interface Of GPUs

GPUDet: A Deterministic GPU Architecture

Warped Register File: A Power Efficient Register File for GPGPUs

GPU Architecture and the Programming Environment

Dynamic Warp Resizing in High-Performance SIMT

Investigating Warp Size Impact in GPUs

Toolchain for programming, simulating and studying the XMT many-core architecture

The Future in Mobile Multicore Computing

Recent source codes

Introduction to Computer Vision

KernelZero: Co-Evolving Proposer and Coder for Continuously Improved GPU Kernel Generation

ACT: Accelerator Compiler Toolkit

pytest-gpu-proof: A Simple Pytest Extension for Local GPU Code Testing

Accelerating the Mitigation of LLM Inference Nondeterminism Across GPU Architectures

nvsass-disassembler

PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving

AutoTuneBench: Trustworthy Measurement for Agent Auto-Tuning of LLM Serving Engines

EinsummableV3 - graph-based computation with tensor operations support

MaxKernel: Intelligent TPU Kernel Engineering Agents

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