high performance computing on graphics processing units: hgpu.org

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The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches

David Tarjan, Kevin Skadron

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Tags: Computer science, Memory, Memory model

August 12, 2011 by hgpu

Performance evaluation and optimization of random memory access on multicores with high productivity

Vaibhav Saxena, Yogish Sabharwal, Pramod Bhatotia

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Tags: Benchmarking, Computer science, CUDA, Memory, nVidia, nVidia Quadro FX 4600, Optimization

August 10, 2011 by hgpu

Cache Miss Analysis for GPU Programs Based on Stack Distance Profile

Tao Tang, Xuejun Yang, Yisong Lin

Tags: Computer science, Memory, Optimization

August 9, 2011 by hgpu

Exploiting SPMD Horizontal Locality

Chunyang Gou, Georgi Gaydadjiev

Tags: Computer science, Memory, Memory model

June 22, 2011 by hgpu

A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits

J.L. Autran, S. Uznanski, S. Martinie, P. Roche, G. Gasiot, D. Munteanu

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Tags: Computer science, CUDA, Fault simulation, Hardware Architecture, Memory, nVidia, Physics, Tesla C1060

June 1, 2011 by hgpu

GPU-based time parallel cache simulator

Junjie Ma, Han Wan, Xiaopeng Gao, Xiang Long

Tags: Algorithms, Computer science, CUDA, Memory, Memory model, nVidia

May 9, 2011 by hgpu

Exploiting GPU On-chip Shared Memory for Accelerating Schedulability Analysis

Swaroop Nunna, Unmesh D. Bordoloi, Samarjit Chakraborty, Petru Eles, Zebo Peng

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Tags: Computer science, CUDA, Memory, nVidia, nVidia GeForce 8800 GTX

May 3, 2011 by hgpu

Exploiting SPMD Horizontal Locality to Improve Memory Efficiency

C. Gou, G. Gaydadjiev

Tags: Computer science, Memory, Performance

April 25, 2011 by hgpu

HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs

Qiang Li, Panyong Zhang, Ninghui Sun

Tags: Cell processor, Computer science, FPGA, Heterogeneous systems, Memory, Performance

April 19, 2011 by hgpu

A Hybrid Analytical DRAM Performance Model

George L. Yuan, Tor M. Aamodt

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Tags: Computer science, CUDA, Hardware Architecture, Memory, nVidia

April 19, 2011 by hgpu

Extending the Scalability of Single Chip Stream Processors with On-chip Caches

Ali Bakhoda, Tor M. Aamodt

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Tags: ATI, Computer science, Hardware Architecture, Memory, nVidia

April 19, 2011 by hgpu

Accelerate Cache Simulation with Generic GPU

Wan Han, Gao Xiaopeng, Wang Zhiqiang

Tags: Algorithms, Computer science, CUDA, Memory, nVidia

April 13, 2011 by hgpu

Over-synchronization in GPU Programs

profile_util: simple C++ library to report memory, timing, thread affinity

Profile Util library: A quick and easy way to get MPI, OpenMP and GPU runtime information

MaC: Mamba CPU performance predictor

MambaCPU: Enhanced Correlation Mining with State Space Models for CPU Performance Prediction

Mixed-precision finite element kernels

Mixed-precision finite element kernels and assembly: Rounding error analysis and hardware acceleration

SHMT: The Simultaneous and Heterogenous Multithreading project

General-Purpose Computing on Tensor Processors

Superpipeline: A Universal Approach for Reducing GPU Memory Usage in Large Models

EnergyUCB-Bandit

Online Energy Optimization in GPUs: A Multi-Armed Bandit Approach

See all packages

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high performance computing on graphics processing units: hgpu.org

The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches

Performance evaluation and optimization of random memory access on multicores with high productivity

Cache Miss Analysis for GPU Programs Based on Stack Distance Profile

Exploiting SPMD Horizontal Locality

A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits

GPU-based time parallel cache simulator

Exploiting GPU On-chip Shared Memory for Accelerating Schedulability Analysis

Exploiting SPMD Horizontal Locality to Improve Memory Efficiency

HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs

A Hybrid Analytical DRAM Performance Model

Extending the Scalability of Single Chip Stream Processors with On-chip Caches

Accelerate Cache Simulation with Generic GPU

Recent source codes

Kokkidio: Kokkos+Eigen - write fast, readable multi-platform code

LLaMA-Inference-Bench

MATAR

Over-synchronization in GPU Programs

profile_util: simple C++ library to report memory, timing, thread affinity

MaC: Mamba CPU performance predictor

Mixed-precision finite element kernels

SHMT: The Simultaneous and Heterogenous Multithreading project

Superpipeline: A Universal Approach for Reducing GPU Memory Usage in Large Models

EnergyUCB-Bandit

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