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Adaptivity in AdaptiveCpp: Optimizing Performance by Leveraging Runtime Information During JIT-Compilation

Aksel Alpay, Vincent Heuveline

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Tags: AMD Radeon Pro VII, ATI, Benchmarking, Computer science, CUDA, HIP, Intel UHD 630, nVidia, nVidia RTX A5000, Package, Performance, SYCL

October 19, 2025 by hgpu

Comparison of different n-body algorithms on various hardware platforms using SYCL

Tim Thüring

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Tags: AMD Radeon Pro VII, Astrophysics, ATI, Computer science, N-body simulation, nVidia, nVidia A100, nVidia GeForce RTX 3090, nVidia Quadro GP100, Package, Physics, SYCL, Thesis

October 15, 2023 by hgpu

Qwen3-235B @ 1M tokens on AMD MI355X

CHUNDER: Enabling Million-Token Qwen3 Serving on AMD ROCm

CUDA++ for the NVIDIA DGX Spark

Reverse Engineering the CUDA Software Stack: A Clean-Room GPU Machine-Code Toolchain for the NVIDIA GB10

ATTUNE: Agentic Throughput Tuning for LLM Training

ATTUNE: Agentic Throughput Tuning for LLM Training

HPCAgent-Bench: A Framework for Sound Benchmarking of Code-Optimizing Agents, Harnesses, and Skills

HPCAgent-Bench: A Framework for Sound Benchmarking of Code-Optimizing Agents, Harnesses, and Skills

Brian2 Atlas

A Unified Intermediate Representation and Execution Architecture for Heterogeneous and Distributed Neural Simulation

AgentGarten: Code Worlds for Evolving Agents

AgentGarten: Code Worlds for Evolving Agents

KernelLens: Automated Triton-to-C++ Compiler for Enterprise Inference Runtimes

KernelLens: Deploying Triton Kernels to C++ Inference Engines

KernelZero: Co-Evolving Proposer and Coder for Continuously Improved GPU Kernel Generation

KernelZero: Co-Evolving Proposer and Coder for Continuously Improved GPU Kernel Generation

Introduction to Computer Vision

Introduction to Computer Vision

ACT: Accelerator Compiler Toolkit

Automatically Generating ML Compiler Backends from Tensor Accelerator ISA Descriptions

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