28798

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures

Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
Politecnico di Milano, Italy
arXiv:2311.17815 [cs.AR], (29 Nov 2023)

@misc{ferrandi2023survey,

   title={A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures},

   author={Fabrizio Ferrandi and Serena Curzel and Leandro Fiorin and Daniele Ielmini and Cristina Silvano and Francesco Conti and Alessio Burrello and Francesco Barchi and Luca Benini and Luciano Lavagno and Teodoro Urso and Enrico Calore and Sebastiano Fabio Schifano and Cristian Zambelli and Maurizio Palesi and Giuseppe Ascia and Enrico Russo and Nicola Petra and Davide De Caro and Gennaro Di Meo and Valeria Cardellini and Salvatore Filippone and Francesco Lo Presti and Francesco Silvestri and Paolo Palazzari and Stefania Perri},

   year={2023},

   eprint={2311.17815},

   archivePrefix={arXiv},

   primaryClass={cs.AR}

}

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In recent years, the field of Deep Learning has seen many disruptive and impactful advancements. Given the increasing complexity of deep neural networks, the need for efficient hardware accelerators has become more and more pressing to design heterogeneous HPC platforms. The design of Deep Learning accelerators requires a multidisciplinary approach, combining expertise from several areas, spanning from computer architecture to approximate computing, computational models, and machine learning algorithms. Several methodologies and tools have been proposed to design accelerators for Deep Learning, including hardware-software co-design approaches, high-level synthesis methods, specific customized compilers, and methodologies for design space exploration, modeling, and simulation. These methodologies aim to maximize the exploitable parallelism and minimize data movement to achieve high performance and energy efficiency. This survey provides a holistic review of the most influential design methodologies and EDA tools proposed in recent years to implement Deep Learning accelerators, offering the reader a wide perspective in this rapidly evolving field. In particular, this work complements the previous survey proposed by the same authors in [203], which focuses on Deep Learning hardware accelerators for heterogeneous HPC platforms.
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