high performance computing on graphics processing units: hgpu.org

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The future of microprocessors

Shekhar Borkar, Andrew A. Chien

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Tags: Computer science, Energy-efficient computing, Hardware Architecture, Review

September 7, 2011 by hgpu

Energy-efficient mechanisms for managing thread context in throughput processors

Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron

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Tags: Computer science, Energy-efficient computing, Hardware Architecture

September 7, 2011 by hgpu

Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators

Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic

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Tags: Benchmarking, Computer science, Hardware Architecture

September 7, 2011 by hgpu

A practical multi-viewer tabletop autostereoscopic display

Gu Ye, Andrei State, Henry Fuchs

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Tags: Computer science, Hardware Architecture, nVidia, nVidia GeForce GTX 295, Rendering

September 4, 2011 by hgpu

An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm Multimedia Stream Processor Core for Mobile Applications

Shao-Yi Chien, You-Ming Tsao, Chin-Hsiang Chang, Yu-Cheng Lin

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Tags: Computer science, Energy-efficient computing, Hardware Architecture

September 3, 2011 by hgpu

TH-1: China’s first petaflop supercomputer

Xuejun Yang, Xiangke Liao, Weixia Xu, Junqiang Song, Qingfeng Hu, Jinshu Su, Liquan Xiao, Kai Lu, Qiang Dou, Juping Jiang, Canqun Yang

Tags: ATI, ATI Radeon HD 4870, Computer science, GPU cluster, Hardware Architecture, Heterogeneous systems

August 25, 2011 by hgpu

WAYPOINT: scaling coherence to thousand-core architectures

John H. Kelm, Matthew R. Johnson, Steven S. Lumettta, Sanjay J. Patel

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Tags: Computer science, Hardware Architecture, Performance

August 24, 2011 by hgpu

Graphics Processing Units for Handhelds

Tomas Akenine-Moller, Jacobs Strom

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Tags: Computer science, Hardware Architecture, Review

August 9, 2011 by hgpu

Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation

Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li

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Tags: Computer science, CUDA, Hardware Architecture, Nonlinear optimization, nVidia, nVidia GeForce 9800 GX2, Optimization

August 6, 2011 by hgpu

Xbox360 Front Side Bus – A 21.6 GB/s End-to-End Interface Design

David Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane, Jeff Johnson

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Tags: Computer science, Hardware Architecture, Review, Xbox 360

August 5, 2011 by hgpu

Cost-effective low-power graphics processing unit for handheld devices

Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seungjin Lee, Hoi-Jun Yoo

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Tags: Computer science, Hardware Architecture, OpenGL, Review

August 2, 2011 by hgpu

Vendors Draw up a New Graphics-Hardware Approach

S.J. Vaughn-Nichols

Tags: Computer science, Hardware Architecture, Review

July 22, 2011 by hgpu

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

SimSYCL: A SYCL Implementation Targeting Development, Debugging, Simulation and Conformance

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

94% on CIFAR-10 in 3.29 Seconds on a Single GPU

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

See all packages

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high performance computing on graphics processing units: hgpu.org

The future of microprocessors

Energy-efficient mechanisms for managing thread context in throughput processors

Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators

A practical multi-viewer tabletop autostereoscopic display

An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm Multimedia Stream Processor Core for Mobile Applications

TH-1: China’s first petaflop supercomputer

WAYPOINT: scaling coherence to thousand-core architectures

Graphics Processing Units for Handhelds

Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation

Xbox360 Front Side Bus – A 21.6 GB/s End-to-End Interface Design

Cost-effective low-power graphics processing unit for handheld devices

Vendors Draw up a New Graphics-Hardware Approach

Recent source codes

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

GPU plugin for PySCF

QArray

Celerity: High-level C++ for Accelerator Clusters

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

OpenMC Monte Carlo Code

Polygeist: C/C++ frontend for MLIR

Parallel Gaussian process with kernel approximation in CUDA

Most viewed papers (last 30 days)