high performance computing on graphics processing units: hgpu.org

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Zorua: Enhancing Programming Ease, Portability, and Performance in GPUs by Decoupling Programming Models from Resource Management

Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko, Samira Khan, Ashish Shrestha, Saugata Ghose, Phillip B. Gibbons, Onur Mutlu

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Tags: Computer science, CUDA, Hardware Architecture, nVidia, Virtualization

February 10, 2018 by hgpu

A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks

Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren

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Tags: CNN, Computer science, CUDA, Deep learning, Energy-efficient computing, FPGA, Hardware Architecture, Neural networks, nVidia, nVidia GeForce GTX Titan X, Performance

February 22, 2017 by hgpu

PipeCNN: An OpenCL-Based FPGA Accelerator for Large-Scale Convolution Neuron Networks

Dong Wang, Jianjing An, Ke Xu

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Tags: CNN, Computer science, Deep learning, DSP, FPGA, Hardware Architecture, Neural networks, OpenCL, Package

November 10, 2016 by hgpu

GPU Performance Modeling and Optimization

Ang Li

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Tags: Computer science, CUDA, Hardware Architecture, nVidia, Performance, PTX, Thesis

October 29, 2016 by hgpu

YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights

Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini

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Tags: Computer science, Computer vision, Deep learning, Hardware Architecture, Neural networks

June 21, 2016 by hgpu

Dissecting GPU Memory Hierarchy through Microbenchmarking

Xinxin Mei, Xiaowen Chu

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Tags: Benchmarking, cache, Computer science, CUDA, Hardware Architecture, nVidia, nVidia GeForce GTX 560 Ti, nVidia GeForce GTX 780, nVidia GeForce GTX 980, Package

September 9, 2015 by hgpu

The More We Share, The More We Have: Improving GPU performance through Register Sharing

Vishwesh Jatala, Jayvant Anantpur, Amey Karkare

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Tags: Computer science, CUDA, GPGPU-sim, Hardware Architecture, nVidia, Performance

March 20, 2015 by hgpu

Mascar: Speeding up GPU Warps by Reducing Memory Pitstops

Ankit Sethia, D. Anoushe Jamshidi, Scott Mahlke

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Tags: Computer science, GPGPU-sim, Hardware Architecture, nVidia, nVidia GeForce GTX 480

February 1, 2015 by hgpu

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

Sparsh Mittal; Jeffrey S. Vetter; Dong Li

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Tags: cache, Compiler, cpu, Energy-efficient computing, GPU, Hardware Architecture, Memory model

January 12, 2015 by sparsh0mittal

A Survey Of Techniques for Managing and Leveraging Caches in GPUs

Sparsh Mittal

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Tags: GPGPU, GPGPU architecture, GPU, Hardware, Hardware Architecture

November 18, 2014 by sparsh0mittal

Understanding the ISA impact on GPU Architecture

Mayank Vinodbhai Kothiya

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Tags: Computer science, CUDA, GPGPU-sim, Hardware Architecture, nVidia, PTX, Tesla, Thesis

July 28, 2014 by hgpu

Fine-grain Task Aggregation and Coordination on GPUs

Marc S. Orr, Bradford M. Beckmann, Steven K. Reinhardt, David A. Wood

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Tags: Computer science, GPGPU-sim, Hardware Architecture, OpenCL, Performance

May 10, 2014 by hgpu

Coccinelle: a C code transformation engine using SmPL for matches, refactorings, and bug fixing

Advances in Semantic Patching for HPC-oriented Refactorings with Coccinelle

DuoReduce: MLIR's benchmark

Hardware-Assisted Software Testing and Debugging for Heterogeneous Computing

Shamrock: Multi-GPU hydrodynamics for astrophysics

The Shamrock code: I- Smoothed Particle Hydrodynamics on GPUs

LLMPerf: GPU Performance Modeling meets Large Language Models

Hercules: A Compiler for Productive Programming of Heterogeneous Systems

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high performance computing on graphics processing units: hgpu.org

Zorua: Enhancing Programming Ease, Portability, and Performance in GPUs by Decoupling Programming Models from Resource Management

A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks

PipeCNN: An OpenCL-Based FPGA Accelerator for Large-Scale Convolution Neuron Networks

GPU Performance Modeling and Optimization

YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights

Dissecting GPU Memory Hierarchy through Microbenchmarking

The More We Share, The More We Have: Improving GPU performance through Register Sharing

Mascar: Speeding up GPU Warps by Reducing Memory Pitstops

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

A Survey Of Techniques for Managing and Leveraging Caches in GPUs

Understanding the ISA impact on GPU Architecture

Fine-grain Task Aggregation and Coordination on GPUs

Recent source codes

Coccinelle: a C code transformation engine using SmPL for matches, refactorings, and bug fixing

DuoReduce: MLIR's benchmark

Shamrock: Multi-GPU hydrodynamics for astrophysics

LLMPerf: GPU Performance Modeling meets Large Language Models

Hercules: A Compiler for Productive Programming of Heterogeneous Systems

Celerity Runtime: High-level C++ for Accelerator Clusters

wgpy: WebGL accelerated numpy-compatible array library for web browser

Microbenchmarking OpenMP target offload with Catch2

SUperman: Highly Efficient Permanent Computation Library

TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework

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