high performance computing on graphics processing units: hgpu.org

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Survey of Domain-Specific Languages for FPGA Computing

Nachiket Kapre, Samuel Bayliss

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Tags: Computer science, DSL, FPGA, survey

July 13, 2016 by hgpu

A Survey of Techniques for Designing and Managing CPU Register File

Sparsh Mittal

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Tags: cpu, Performance, Register file, survey

July 8, 2016 by sparsh0mittal

A Survey of Cache Bypassing Techniques

Sparsh Mittal

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Tags: cache bypassing, cpu, CPU-GPU heterogeneous system, DRAM, GPU, Memory, non-volatile memory, survey

April 29, 2016 by sparsh0mittal

Fluid Simulation by the Smoothed Particle Hydrodynamics Method: A Survey

T. Weaver, Z. Xiao

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Tags: CUDA, Fluid dynamics, Fluid simulation, nVidia, survey

April 16, 2016 by hgpu

A Survey of Recent Prefetching Techniques for Processor Caches

Sparsh Mittal

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Tags: cache, cpu, Hardware, Paper, Performance, Prefetching, Research, Software, survey

March 25, 2016 by sparsh0mittal

A Survey of Techniques for Architecting and Managing GPU Register File

Sparsh Mittal

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Tags: Energy efficiency, GPU, nVidia, Performance, Power, Register file, Reliability, Research, survey

March 22, 2016 by sparsh0mittal

A Survey Of Techniques for Approximate Computing

Sparsh Mittal

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Tags: Approximate computing and storage, cpu, FPGA, GPU, Neural networks, Power management, survey

January 14, 2016 by sparsh0mittal

A Survey Of Techniques for Cache Locking

Sparsh Mittal

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Tags: cache, cache partitioning, cpu, GPU, multitasking, real time systems, survey, WCET

December 15, 2015 by sparsh0mittal

A Survey Of Architectural Techniques for Managing Process Variation

Sparsh Mittal

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Tags: cache, computer architecture, cpu, DVFS, GPU, Memory, survey

December 6, 2015 by sparsh0mittal

A Survey Of Techniques for Architecting and Managing Asymmetric Multicore Processors

Sparsh Mittal

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Tags: asymmetric multicore processor (AMP), big/little system, classification, heterogeneous multicore architecture, reconfigurable AMP, Review, survey

November 13, 2015 by sparsh0mittal

A Survey Of Architectural Techniques for Near-Threshold Computing

Sparsh Mittal

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Tags: cpu, Energy-efficient computing, low voltage computing, Memory, Power-efficient computing, survey

September 7, 2015 by sparsh0mittal

A Survey Of Techniques for Architecting DRAM Caches

Sparsh Mittal, Jeffrey Vetter

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Tags: 3D DRAM, bandwidth, cpu, die-stacking, GPU, Memory, survey

August 7, 2015 by sparsh0mittal

torchPDLP: Primal-Dual Linear Programming in PyTorch. In collaboration with AMD and IPAM

Accelerating a Linear Programming Algorithm on AMD GPUs

Benchmarks for Dissecting CPU-GPU Unified Physical Memory on AMD MI300A APUs

Dissecting CPU-GPU Unified Physical Memory on AMD MI300A APUs

kvcached: Elastic KV cache for dynamic GPU sharing and efficient multi-LLM inference

Towards Efficient and Practical GPU Multitasking in the Era of LLM

Bandicoot: C++ library for GPU accelerated linear algebra

Bandicoot: A Templated C++ Library for GPU Linear Algebra

Luthier: Bridging Auto-Tuning and Vendor Libraries for Efficient Deep Learning Inference

Fused Kernel Library (FKL)

The Fused Kernel Library: A C++ API to Develop Highly-Efficient GPU Libraries

GPUHammer: Rowhammer Attacks on GPU Memories are Practical

Block: Balance Loader of LLM Serving with Context, Knowledge and Predictive Scheduling

Block: Balancing Load in LLM Serving with Context, Knowledge and Predictive Scheduling

SIGMo: Scalable Isomorphism Graph Matching on GPUs

SIGMo: High-Throughput Batched Subgraph Isomorphism on GPUs for Molecular Matching

DGEMM without FP64 Arithmetic - using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme

DGEMM without FP64 Arithmetic – using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme

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high performance computing on graphics processing units: hgpu.org

Survey of Domain-Specific Languages for FPGA Computing

A Survey of Techniques for Designing and Managing CPU Register File

A Survey of Cache Bypassing Techniques

Fluid Simulation by the Smoothed Particle Hydrodynamics Method: A Survey

A Survey of Recent Prefetching Techniques for Processor Caches

A Survey of Techniques for Architecting and Managing GPU Register File

A Survey Of Techniques for Approximate Computing

A Survey Of Techniques for Cache Locking

A Survey Of Architectural Techniques for Managing Process Variation

A Survey Of Techniques for Architecting and Managing Asymmetric Multicore Processors

A Survey Of Architectural Techniques for Near-Threshold Computing

A Survey Of Techniques for Architecting DRAM Caches

Recent source codes

torchPDLP: Primal-Dual Linear Programming in PyTorch. In collaboration with AMD and IPAM

Benchmarks for Dissecting CPU-GPU Unified Physical Memory on AMD MI300A APUs

kvcached: Elastic KV cache for dynamic GPU sharing and efficient multi-LLM inference

Bandicoot: C++ library for GPU accelerated linear algebra

Luthier: Bridging Auto-Tuning and Vendor Libraries for Efficient Deep Learning Inference

Fused Kernel Library (FKL)

GPUHammer: Rowhammer Attacks on GPU Memories are Practical

Block: Balance Loader of LLM Serving with Context, Knowledge and Predictive Scheduling

SIGMo: Scalable Isomorphism Graph Matching on GPUs

DGEMM without FP64 Arithmetic - using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme

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