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Porting Batched Iterative Solvers onto Intel GPUs with SYCL

Phuong Nguyen, Pratik Nayak, Hartwig Anzt

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Tags: Computer science, CUDA, Intel, Intel Data Center GPU Max 1550, nVidia, nVidia A100, nVidia H100, Package, performance portability, Physics, SYCL

August 20, 2023 by hgpu

CUDA-L2: Surpassing cuBLAS Performance for Matrix Multiplication through Reinforcement Learning

CUDA-L2: Surpassing cuBLAS Performance for Matrix Multiplication through Reinforcement Learning

BoltzGen:Toward Universal Binder Design

BoltzGen:Toward Universal Binder Design

cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolution

cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolution

MATLAB Tensor Core models

Accurate Models of NVIDIA Tensor Cores

TritonForge: Transform PyTorch Operations into Optimized GPU Kernels with LLMs

TritonForge: Profiling-Guided Framework for Automated Triton Kernel Optimization

RLTune: Hybrid Learning and Optimization-Based Dynamic Scheduling for DL Workloads on Heterogeneous GPU Clusters

Hybrid Learning and Optimization-Based Dynamic Scheduling for DL Workloads on Heterogeneous GPU Clusters

tritonBLAS: A Lightweight Triton-based General Matrix Multiplication (GEMM) Library

tritonBLAS: Triton-based Analytical Approach for GEMM Kernel Parameter Selection

hls4ml: Machine learning on FPGAs using HLS

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

NVIDIA Nemotron Parse 1.1

NVIDIA Nemotron Parse 1.1

ThunderKittens: Tile primitives for speedy kernels

ParallelKittens: Systematic and Practical Simplification of Multi-GPU AI Kernels

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