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CLUEstering: a high-performance density-based clustering library for scientific computing

Simone Balducci

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Tags: Astrophysics, ATI, Clustering, CUDA, FPGA, HIP, Machine learning, nVidia, Package, performance portability, Physics, Python, Tesla T4, Thesis

December 1, 2024 by hgpu

Scaling SU(2) to 1000 GPUs using HiRep

Sofie Martins, Erik Kjellgren, Emiliano Molinaro, Claudio Pica, Antonio Rago

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Tags: AMD Radeon Instinct MI250X, ATI, CUDA, HEP, High Energy Physics - Lattice, HIP, Monte Carlo simulation, nVidia, nVidia H100, Package, Physics

December 1, 2024 by hgpu

Performance portability via C++ PSTL, SYCL, OpenMP, and HIP: the Gaia AVU-GSR case study

Giulio Malenza, Valentina Cesare, Marco Edoardo Santimaria, Robert Birke, Alberto Vecchiato, Ugo Becciani, Marco Aldinucci

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Tags: AMD Radeon Instinct MI250X, Astrophysics, ATI, Computer science, CUDA, HIP, HPC, nVidia, nVidia A100, nVidia H100, nVidia V100, OpenMP, Package, Performance, performance portability, SYCL, Tesla T4

November 24, 2024 by hgpu

On a Simplified Approach to Achieve Parallel Performance and Portability Across CPU and GPU Architectures

Nathaniel Morgan, Caleb Yenusah, Adrian Diaz, Daniel Dunning,Jacob Moore,Erin Heilman, Calvin Roth, Evan Lieberman, Steven Walton, Sarah Brown, Daniel Holladay, Marko Knezevic, Gavin Whetstone, Zachary Baker, Robert Robey

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Tags: Computer science, CUDA, Fortran, HIP, nVidia, Package, performance portability, Pthreads

November 10, 2024 by hgpu

Testing GPU Numerics: Finding Numerical Differences Between NVIDIA and AMD GPUs

Anwar Hossain Zahid, Ignacio Laguna, Wei Le

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Tags: AMD Radeon Instinct MI250, ATI, Computer science, CUDA, HIP, Numerical Analysis, nVidia, nVidia V100, Programming Languages

October 20, 2024 by hgpu

Understanding Data Movement in AMD Multi-GPU Systems with Infinity Fabric

Gabin Schieffer, Ruimin Shi, Stefano Markidis, Andreas Herten, Jennifer Faj, Ivy Peng

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Tags: AMD, AMD Radeon Instinct MI250X, ATI, Computer science, HIP, Machine learning, Memory, Performance

October 6, 2024 by hgpu

Event-Based OpenMP Tasks for Time-Sensitive GPU-Accelerated Systems

Cyril Cetre, Chenle Yu, Sara Royuela, Rémi Barrere, Eduardo Quiñones, Damien Gratadour

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Tags: AMD Radeon Instinct MI100, ATI, Computer science, CUDA, HIP, HPC, nVidia, nVidia A100, Performance

October 6, 2024 by hgpu

HiCCL: A Hierarchical Collective Communication Library

Mert Hidayetoglu, Simon Garcia de Gonzalo, Elliott Slaughter, Pinku Surana, Wen-mei Hwu, William Gropp, Alex Aiken

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Tags: AMD Radeon Instinct MI250X, ATI, Computer science, CUDA, HIP, nVidia, nVidia A100, Package, Performance, SYCL

August 18, 2024 by hgpu

HIPRT: A Ray Tracing Framework in HIP

Daniel Meister, Paritosh Kulkarni, Aaryaman Vasishta, Takahiro Harada

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Tags: 3D Graphics and Realism, AMD Radeon Pro W7900, ATI, HIP, Package, Raytracing, Rendering, Vulkan

August 14, 2024 by hgpu

Evaluating Operators in Deep Neural Networks for Improving Performance Portability of SYCL

Zheming Jin

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Tags: Benchmarking, Computer science, CUDA, HIP, Machine learning, Neural networks, nVidia, nVidia GeForce RTX 2080, nVidia GeForce RTX 3090, nVidia H100, oneAPI, Performance, performance portability, SYCL, Tesla A100, Tesla V100

August 14, 2024 by hgpu

A Comparison of OpenCL, CUDA, and HIP as Compilation Targets for a Functional Array Language

Troels Henriksen

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Tags: AMD Radeon Instinct MI100, ATI, Code generation, Computer science, CUDA, HIP, nVidia, nVidia A100, OpenCL, Package, Programming Languages

July 28, 2024 by hgpu

Bringing Auto-tuning to HIP: Analysis of Tuning Impact and Difficulty on AMD and Nvidia GPUs

Milo Lurati, Stijn Heldens, Alessio Sclocco, Ben van Werkhoven

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Tags: AMD Radeon Instinct MI250X, AMD Radeon Pro W6600, ATI, Computer science, CUDA, HIP, nVidia, nVidia A100, nVidia RTX A4000, Package, Performance, Python

July 28, 2024 by hgpu

CFAL-bench

Comparing Parallel Functional Array Languages: Programming and Performance

Efficient Graph Embedding at Scale: Optimizing CPU-GPU-SSD Integration

Can Large Language Models Predict Parallel Code Performance?

Data-efficient LLM Fine-tuning for Code Generation

DeepSpeed is a deep learning optimization library that makes distributed training and inference easy, efficient, and effective.

DeepCompile: A Compiler-Driven Approach to Optimizing Distributed Deep Learning Training

Large Language Model Powered C-to-CUDA Code Translation: A Novel Auto-Parallelization Framework

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high performance computing on graphics processing units: hgpu.org

CLUEstering: a high-performance density-based clustering library for scientific computing

Scaling SU(2) to 1000 GPUs using HiRep

Performance portability via C++ PSTL, SYCL, OpenMP, and HIP: the Gaia AVU-GSR case study

On a Simplified Approach to Achieve Parallel Performance and Portability Across CPU and GPU Architectures

Testing GPU Numerics: Finding Numerical Differences Between NVIDIA and AMD GPUs

Understanding Data Movement in AMD Multi-GPU Systems with Infinity Fabric

Event-Based OpenMP Tasks for Time-Sensitive GPU-Accelerated Systems

HiCCL: A Hierarchical Collective Communication Library

HIPRT: A Ray Tracing Framework in HIP

Evaluating Operators in Deep Neural Networks for Improving Performance Portability of SYCL

A Comparison of OpenCL, CUDA, and HIP as Compilation Targets for a Functional Array Language

Bringing Auto-tuning to HIP: Analysis of Tuning Impact and Difficulty on AMD and Nvidia GPUs

Recent source codes

CFAL-bench

Efficient Graph Embedding at Scale: Optimizing CPU-GPU-SSD Integration

Can Large Language Models Predict Parallel Code Performance?

PELSI: Power-Efficient Layer-Switched Inference

Ouroboros: Virtualized Queues for dynamic memory management

MSCCL++: A GPU-driven communication stack for scalable AI applications

Benchmark compute shader of Unity against InteropUnityCUDA

Data-efficient LLM Fine-tuning for Code Generation

DeepSpeed is a deep learning optimization library that makes distributed training and inference easy, efficient, and effective.

Large Language Model Powered C-to-CUDA Code Translation: A Novel Auto-Parallelization Framework

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