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SYCL in the Edge: Performance Evaluation for Heterogeneous Acceleration

Youssef Faqir-Rhazoui, Carlos García

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Tags: Computer science, CUDA, FPGA, Heterogeneous systems, nVidia, nVidia Jetson Nano, Optical flow, Package, SYCL

October 22, 2023 by hgpu

Strega: An HTTP Server for FPGAs

Fabio Maschi, Gustavo Alonso

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Tags: Computer science, FPGA, OpenCL, Package

October 15, 2023 by hgpu

Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis Workflow

Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan

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Tags: Code generation, Computer science, FPGA, HLS, OpenCL, Package, Performance

October 8, 2023 by hgpu

Improving the Efficiency of OpenCL Kernels through Pipes

Mostafa Eghbali Zarch, Michela Becchi

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Tags: Computer science, FPGA, OpenCL, Performance, performance portability

September 17, 2023 by hgpu

Unified Shared Memory: Friend or Foe?

Juan Fumero Alfonso, Florin-Gabriel Blanaru, Athanasios Stratikopoulos, Steve Dohrmann, Sandhya Viswanathan, Christos-Efthymios Kotselidis

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Tags: Code generation, Computer science, CUDA, FPGA, Heterogeneous systems, Java, Memory, nVidia, nVidia GeForce RTX 3070, OpenCL

September 17, 2023 by hgpu

Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs

Gabriel Rodriguez-Canal, Nick Brown, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus

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Tags: Computer science, Fortran, FPGA, HLS, HPC, OpenCL, Performance

September 6, 2023 by hgpu

eGPU: A 750 MHz Class Soft GPGPU for FPGA

Martin Langhammer, George Constantinides

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Tags: Computer science, DSP, FPGA, Hardware Architecture

July 24, 2023 by hgpu

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

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Tags: Compilers, Computer science, CUDA, Design space exploration, DSP, FPGA, Heterogeneous systems, nVidia, nVidia GeForce GTX 1660, nVidia GeForce RTX 3080 Ti, Package, Thesis

June 25, 2023 by hgpu

minimap2-fpga: Integrating hardware-accelerated chaining for efficient end-to-end long-read sequence mapping

Kisaru Liyanage, Hiruna Samarakoon, Sri Parameswaran, Hasindu Gamaarachchi

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Tags: Bioinformatics, Biology, Cloud, FPGA, OpenCL, Package, Sequence alignment

June 11, 2023 by hgpu

Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs

Fumiya Kono, Naohito Nakasato, Maho Nakata

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Tags: Benchmarking, Computer science, Extended precision, FPGA, Matrix multiplication, OpenCL

June 11, 2023 by hgpu

Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads

Yanwen Xu, Ang Li, Tyler Sorensen

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Tags: Benchmarking, Computer science, CUDA, FPGA, Heterogeneous systems, HLS, Intel UHD 630, nVidia, nVidia Jetson AGX Xavier, nVidia Jetson Nano, Package, Performance, SYCL

May 7, 2023 by hgpu

Task parallelism-based architectures on FPGA to optimize the energy efficiency of AI at the edge

Rafael Gadea-Gironés, Jorge Fe, Jose M. Monzo

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Tags: Artificial intelligence, Computer science, Energy-efficient computing, FPGA, Neural networks, OpenCL

April 2, 2023 by hgpu

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

SimSYCL: A SYCL Implementation Targeting Development, Debugging, Simulation and Conformance

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

94% on CIFAR-10 in 3.29 Seconds on a Single GPU

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

See all packages

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high performance computing on graphics processing units: hgpu.org

SYCL in the Edge: Performance Evaluation for Heterogeneous Acceleration

Strega: An HTTP Server for FPGAs

Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis Workflow

Improving the Efficiency of OpenCL Kernels through Pipes

Unified Shared Memory: Friend or Foe?

Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs

eGPU: A 750 MHz Class Soft GPGPU for FPGA

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs

Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads

Task parallelism-based architectures on FPGA to optimize the energy efficiency of AI at the edge

Recent source codes

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

GPU plugin for PySCF

QArray

Celerity: High-level C++ for Accelerator Clusters

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

OpenMC Monte Carlo Code

Polygeist: C/C++ frontend for MLIR

Parallel Gaussian process with kernel approximation in CUDA

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