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A novel FPGA-based SVM classifier

Markos Papadonikolakis, Christos-Savvas Bouganis

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Tags: Computational Complexity, Computer science, FPGA, Heterogeneous systems

August 15, 2011 by hgpu

Network-on-Chip Hardware Accelerators for Biological Sequence Alignment

Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman

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Tags: Algorithms, Bioinformatics, Biology, FPGA, Sequence alignment

August 12, 2011 by hgpu

Pricing the American Option Using Reconfigurable Hardware

Chris Wynnyk, Malik Magdon-Ismail

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Tags: Algorithms, CUDA, Finance, Finite difference, FPGA, nVidia, Tesla S1070

August 10, 2011 by hgpu

Hardware accelerators for biocomputing: A survey

Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande

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Tags: Biology, Cell processor, CUDA, FPGA, Molecular dynamics, nVidia, nVidia GeForce 7800 GTX, Performance, Review, Sequence alignment

August 7, 2011 by hgpu

Exploring reconfigurable architectures for explicit finite difference option pricing models

Qiwei Jin, David B. Thomas, Wayne Luk

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Tags: CUDA, Finance, Finite difference, FPGA, nVidia, nVidia GeForce 8600 GT, Tesla C1060

August 3, 2011 by hgpu

Unifying stream based and reconfigurable computing to design application accelerators

Bruno Francisco, Frederico Pratas, Leonel Sousa

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Tags: Bioinformatics, Biology, Computer science, Data parallelism, FPGA, nVidia, nVidia GeForce GTX 285

August 2, 2011 by hgpu

Potential contribution of CNN-based solving of stiff ODEs and PDEs to enabling real-time Computational Engineering

J.C. Chedjou, K. Kyamakya, U.A. Khan, M.A. Latif

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Tags: Cellular neural networks, CNN, Computational Engineering, Computer science, Differential equations, DSP, FPGA, Maxwell's equations, Neural networks, ODEs, Optimization, Ordinary differential equations, Partial differential equations, PDEs

August 2, 2011 by hgpu

Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture

Sean Whitty, Henning Sahlbach, Rolf Ernst, Wolfram Putzke-Roming

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Tags: Algorithms, FPGA, Heterogeneous systems, Image processing

August 1, 2011 by hgpu

Towards an embedded biologically-inspired machine vision processor

Vinay Sriram, David Cox, Kuen Hung Tsoi, Wayne Luk

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Tags: Algorithms, ASIC, Computer science, Computer vision, FPGA, Image recognition, nVidia, Tesla C1060

August 1, 2011 by hgpu

A parallel accelerator for semantic search

Abhinandan Majumdar, Srihari Cadambi, Srimat T. Chakradhar, Hans Peter Graf

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Tags: Algorithms, Computer science, CUDA, Data parallelism, Databases, FPGA, nVidia, Semantic indexing, Tesla C1060

July 30, 2011 by hgpu

FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks

David B. Thomas, Wayne Luk

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Tags: Computer science, CUDA, FPGA, Neural networks, nVidia, nVidia GeForce GT 200, Performance

July 29, 2011 by hgpu

Real-time Semi-Global Matching on the CPU

Stefan K. Gehrig, Clemens Rabe

Tags: Algorithms, Computer science, Computer vision, FPGA, nVidia, nVidia GeForce 8800 Ultra, Performance, Stereo vision

July 28, 2011 by hgpu

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

SimSYCL: A SYCL Implementation Targeting Development, Debugging, Simulation and Conformance

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

94% on CIFAR-10 in 3.29 Seconds on a Single GPU

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

See all packages

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high performance computing on graphics processing units: hgpu.org

A novel FPGA-based SVM classifier

Network-on-Chip Hardware Accelerators for Biological Sequence Alignment

Pricing the American Option Using Reconfigurable Hardware

Hardware accelerators for biocomputing: A survey

Exploring reconfigurable architectures for explicit finite difference option pricing models

Unifying stream based and reconfigurable computing to design application accelerators

Potential contribution of CNN-based solving of stiff ODEs and PDEs to enabling real-time Computational Engineering

Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture

Towards an embedded biologically-inspired machine vision processor

A parallel accelerator for semantic search

FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks

Real-time Semi-Global Matching on the CPU

Recent source codes

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

GPU plugin for PySCF

QArray

Celerity: High-level C++ for Accelerator Clusters

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

OpenMC Monte Carlo Code

Polygeist: C/C++ frontend for MLIR

Parallel Gaussian process with kernel approximation in CUDA

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